The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIGS. 1, 2A and 2B, nonvolatile (NV) semiconductor memory 10 may include flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM, multi-state memory, etc. The NV semiconductor memory 10 may include one or more arrays 16 that may each be arranged on one or more memory chips. The arrays 16 may include data structures, such as blocks and pages. The arrays 16 may therefore be arranged as B blocks 18-1, 18-2, . . . , and 18-B (collectively referred to as blocks 18).
In FIG. 2A, each block 18 includes P pages 20-1, 20-2, . . . , and 20-P (collectively referred to as pages 20). In FIG. 2B, each page 20 may include memory cells that are associated with a data portion 24 and may include other memory cells that are associated with an overhead data portion 26, such as error correcting code (ECC) data or other (O) overhead data.
Referring now to FIG. 2C, a memory drive may include one or more arrays 16-1, 16-2, . . . , and 16-C (collectively referred to as arrays 16) and each include blocks 18. Usually, the control module addresses the memory drive according to a hardwired physical block size. Pages 20 in the blocks 18 may also have a hardwired physical page size and may therefore be referred to as physical pages. The number of memory cells in the data and overhead portions of the pages 20 may also be hardwired.
For example only, a NAND flash array may include 2048 blocks for a total of 2 Gigabytes (GB) of memory. Each block may include 128 kilobytes (KB) in 64 pages. Each page 20 may include 2112 bytes. Of the 2112 bytes, 2048 bytes may be associated with the data portion and 64 bytes may be associated with the overhead portion. Each memory cell may store a bit.
The memory control module erases pages 20 and blocks 18 according to predetermined erase blocks 29-1, 29-2, . . . , and 29-R (collectively referred to as erase blocks 29). The memory control module generally requires data in an entire erase block to be erased simultaneously.
A host device may initiate a read operation and provide data files to the memory control module that are arranged in multiples of allocation units (AUs) of predefined size that fit in a physical block. AUs correspond to the smallest logical amount of memory space that can be allocated by the control module to store a file and may therefore be referred to as logical pages. Groupings of logical pages may be referred to as logical blocks.
When a write command is issued, data is sent in multiples of logical block size to the memory control module. The memory control module allocates the exact number of physical pages 20 to accommodate the logical pages. Even when ECC is used on logical page data, the number of parity bits are kept within the number of spare bits per overhead portion of a respective physical page. Therefore, one (ECC) coded logical page fits in an integer number of physical pages, and one coded logical block fits within an integer number of physical blocks.